1. Field of the Invention
The present invention relates generally to patterning techniques and, more particularly, to an improved patterning process useful for the metallization of highly efficient photovoltaic cells, in the formation of X-ray lithography masks in the sub half-micron range, and in the fabrication of VLSI and MMIC devices.
2. The Prior Art
In the technology of today, the key words appear to be "speed," "effiiency" and "miniaturization". This is especially true in photovoltaics, in X-ray lithography and in electronic devices.
During the past decade or so, photovoltaic cells with conversion efficiencies of about 27% (AM1) have been achieved. These include single-crystal GaAs solar cells, in particular highly efficient GaAs concentrator cells, point-contact back junction cells and cascade photovoltaic cells. See U.S. Pat. No. 4,392,297, Little, "Process of Making Thin Film High Efficiency Solar Cells," assigned to a common assignee; J. G. Werthen, "26% Efficient GaAs Concentrator Cells," Rec. of the 13th Photovoltaic Concentrator Project Integration Meeting, Sandia Report SAND85-0791/1, 1985, p. 160; M. A. Green, M. Taouk, A. W. Blakers, S. Narayanan, J. Zhao, and P. Campbell, "23.6% Efficient Low Resistivity Silicon Concentrator Solar Cell," Appl. Phys. Lett. 49, 194 (1986); J. M. Gee, R. Y. Loo, S. S. Kameth, and R. C. Knechti, "A GaAs/Si Mechanically Stacked, Multi-junction Solar Cell," Rec. of the 18th IEEE Photovoltaic Specialists Conference, 1985; and R. M. Swanson, "Point-contact Solar Cells: Modeling and Experiment," Solar Cells 17, 85 (1986). A limiting factor in achieving higher conversion efficiencies in solar cells involves the losses experienced attendant on the metallization of the cells. These metallization losses prevent efficient operation at the high intensities (i.e., greater than 10 W/cm.sup.2, equivalent to about 100 suns) at which the economic benefits of employing such highly efficient photovoltaic cells are realized.
Metallization of a solar cell must satisfy several conflicting requirements, such as: 1. the metal coverage of the front surface of the solar cell must be low in order to minimize losses due to the shadowing of the cell surface; 2. the distance from any point on the cell surface to the nearest metallization element must be short in order to minimize sheet resistance losses in the front surface layer; 3. resistance along the wire mesh and the conductor bus must be low; and 4. contact resistance between the metallization element and the semiconductor front surface must be low in order to minimize power losses due to these resistances. Thus, the total fraction of solar cell power lost is the sum of the fractional power losses due to sheet resistance, wire mesh and conductor bus resistances, and contact resistance, in addition to the above-mentioned shadowing.
Among these four, the principal power loss in a solar cell is optical shadow loss introduced by the front surface metallization. As known, a compromise exists between optical shadow loss and series resistance loss in the front contact, with the optical concentration design often determined accordingly. In general, these conflicting requirements are best satisfied by a metallic grid pattern comprising many fine, thin wires rather than fewer wider wires. This is particularly true for highly efficient solar cells, where narrow (about 3 microns) closely spaced (on about 30 to about 60 micron centers) lines are preferred. The power losses in a solar cell due to the several resistances and the shadowing can be derived from power criteria. With the aid of these criteria, the size and shape of the mesh can be optimized.
The fraction of power lost (Pshadow) in a solar cell due to the shadowing of the solar cell area is best expressed by the fractional cell area that is covered: Pshadow=A.sub.m /A.sub.T, where A.sub.m denotes the area of the metal and A.sub.T denotes the total area. In instances in which the wire grid lines are regularly spaced and are parallel, Pshadow is the ratio of the thickness of the wire "T" and the center-to-center spacing "W," with the fraction of power loss given by: EQU Pshadow=T/W,
The width of the open mesh element is determined by the wire spacing per cm and the thickness of the gridline wire.
The point-contact solar cell, described by R. M. Swanson in his article quoted above, is the only exception in that it has no optical shadow loss, due to its construction. However, if the point-contact solar cell is operated at high concentrations (at greater than 100 suns, i.e., at intensities in excess of 10 W/cm.sup.2), precisely for which such a point-contact cell has been designed, its conversion efficiency becomes limited by series resistance in the back interdigitated collection grid. Thus, in the case of the point-contact solar cell, the design compromise is between series resistance and the necessary geometrical limitations imposed by the back junction interdigitated configuration.
In X-ray lithography and, in particular, in the formation of X-ray lithography masks in the sub half-micron range, it is imperative that the X-ray absorber walls be vertical so as to avoid penumbral shadow and thus to provide that degree of resolution and linewidth control necessary for making quality high-density electronic components and the like. X-ray lithography masks are required in X-ray lithography systems for making microcircuits, memories and other high-density electronic components. An X-ray lithography mask is a thin-film X-ray transparent membrane that is in tension and which has been patterned with an X-ray absorber material. The X-ray mask must be flat and possess good dimensional stability, tensile strength and tensile stress, and exhibit low defect densities, both when it is patterned and thereafter, in order to yield quality high-density electronic components. The adverse effects of non-vertical absorber walls on blur and linewidth control are described by R. P. Jaeger and B. L. Heflinger, in their article: "Linewidth Control in X-ray Lithography: the Influence of the Penumbral Shadow," SPIE 471, Electron-Beam, X-ray, and Ion-Beam Techniques for Submicrometer Lithographies III (1984), 110.
Basically, two methods in the art of X-ray lithography mask making have evolved: a "subtraction" method and an "additive" method. The subtraction method of X-ray lithography mask making essentially involves ion-etching through a patterned resist. The absorber wall profiles produced by the subtraction method, however, exhibit slopes which are off the vertical by 15 to 30 degrees. While such absorber wall profiles may have sufficed in the past for X-ray lithography purposes, they are clearly incompatible with sub half-micron X-ray lithography today. See A. R. Shimkunas and S. A. Harrell, "X-ray Mask Technology," SPIE 537, p. 206, 1985.
Workers at AT&T Bell Laboratories have gone the route of the additive method of X-ray lithography mask making in their efforts to obtain straight-walled half micron lines. In this additive method, the AT&T Bell workers have employed "fountain plating" through a straight-walled stencil. The formation of such a straight-walled stencil, however, requires a tri-level resist system to begin with. And, during the fountain plating itself through this straight-walled stencil, they noticed that they had to maintain careful control of the plating current so as to keep residual stress in the plated X-ray absorber walls near zero and also to maintain sub-micron grain size in those X-ray absorber walls. See G. E. Georgiou, C. A. Jankoski, T. A. Palumbo, "DC Electroplating of Sub-micron Gold Patterns on X-ray Masks," SPIE 471, p. 96, 1984. The commercial acceptance of their method, therefore, has yet to be proven.
The current state of affairs thus requires sub half-micron X-ray lithography masks with vertical X-ray absorber walls for the fabrication of reliable high-density electronic components, microcircuits, miniature memories and devices incorporating such components, microcircuits and memories. Such devices include the Very Large Scale Integration devices (VLSI), the ultra large scale integration devices (ULSI) and the Monolithic Microwave Integrated Circuits (MMIC), to mention but a few. The very quality and performance of these devices, so widely employed in our space exploration and defensive systems, depend in turn, on the quality of the fabrication methods employed during their manufacture.